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Espressif Systems /ESP32-P4 /MCPWM0 /INT_ENA

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Interpret as INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMER0_STOP_INT_ENA)TIMER0_STOP_INT_ENA 0 (TIMER1_STOP_INT_ENA)TIMER1_STOP_INT_ENA 0 (TIMER2_STOP_INT_ENA)TIMER2_STOP_INT_ENA 0 (TIMER0_TEZ_INT_ENA)TIMER0_TEZ_INT_ENA 0 (TIMER1_TEZ_INT_ENA)TIMER1_TEZ_INT_ENA 0 (TIMER2_TEZ_INT_ENA)TIMER2_TEZ_INT_ENA 0 (TIMER0_TEP_INT_ENA)TIMER0_TEP_INT_ENA 0 (TIMER1_TEP_INT_ENA)TIMER1_TEP_INT_ENA 0 (TIMER2_TEP_INT_ENA)TIMER2_TEP_INT_ENA 0 (FAULT0_INT_ENA)FAULT0_INT_ENA 0 (FAULT1_INT_ENA)FAULT1_INT_ENA 0 (FAULT2_INT_ENA)FAULT2_INT_ENA 0 (FAULT0_CLR_INT_ENA)FAULT0_CLR_INT_ENA 0 (FAULT1_CLR_INT_ENA)FAULT1_CLR_INT_ENA 0 (FAULT2_CLR_INT_ENA)FAULT2_CLR_INT_ENA 0 (CMPR0_TEA_INT_ENA)CMPR0_TEA_INT_ENA 0 (CMPR1_TEA_INT_ENA)CMPR1_TEA_INT_ENA 0 (CMPR2_TEA_INT_ENA)CMPR2_TEA_INT_ENA 0 (CMPR0_TEB_INT_ENA)CMPR0_TEB_INT_ENA 0 (CMPR1_TEB_INT_ENA)CMPR1_TEB_INT_ENA 0 (CMPR2_TEB_INT_ENA)CMPR2_TEB_INT_ENA 0 (TZ0_CBC_INT_ENA)TZ0_CBC_INT_ENA 0 (TZ1_CBC_INT_ENA)TZ1_CBC_INT_ENA 0 (TZ2_CBC_INT_ENA)TZ2_CBC_INT_ENA 0 (TZ0_OST_INT_ENA)TZ0_OST_INT_ENA 0 (TZ1_OST_INT_ENA)TZ1_OST_INT_ENA 0 (TZ2_OST_INT_ENA)TZ2_OST_INT_ENA 0 (CAP0_INT_ENA)CAP0_INT_ENA 0 (CAP1_INT_ENA)CAP1_INT_ENA 0 (CAP2_INT_ENA)CAP2_INT_ENA

Description

Interrupt enable register

Fields

TIMER0_STOP_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
TIMER1_STOP_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
TIMER2_STOP_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
TIMER0_TEZ_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
TIMER1_TEZ_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
TIMER2_TEZ_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
TIMER0_TEP_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
TIMER1_TEP_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
TIMER2_TEP_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
FAULT0_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
FAULT1_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
FAULT2_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
FAULT0_CLR_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
FAULT1_CLR_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
FAULT2_CLR_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
CMPR0_TEA_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
CMPR1_TEA_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
CMPR2_TEA_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
CMPR0_TEB_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
CMPR1_TEB_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
CMPR2_TEB_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
TZ0_CBC_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0.
TZ1_CBC_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1.
TZ2_CBC_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2.
TZ0_OST_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0.
TZ1_OST_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1.
TZ2_OST_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2.
CAP0_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
CAP1_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
CAP2_INT_ENA

Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd